1. Field of the Invention
The present invention relates to semiconductor device assemblies employing multi-layered lead frames and more, specifically, to semiconductor device assemblies disposing a decoupling capacitor in a close, substantially co-extensive relationship with a semiconductor device bearing an integrated circuit.
2. Background of Related Art
There is a continued trend in the computer industry toward ever-higher speed integrated circuit (IC) assemblies based upon semiconductor device technology. Such high signal speeds, however, lack utility unless accompanied by suppression of system noise to an acceptable level. The trend toward lower operational signal voltages in combination with such high speeds exacerbates noise problems.
At state-of-the art operational speeds, signal propagation delays, switching noise, and crosstalk between signal conductors resulting from mutual inductance and self inductance phenomena of the conductive paths all become significant to signal degradation. Mutual inductance results from an interaction between magnetic fields created by signal currents flowing to and from a lead frame-mounted, packaged semiconductor device through the leads or xe2x80x9clead fingers,xe2x80x9d while self inductance results from the interaction of the foregoing fields with magnetic fields created by oppositely-directed currents flowing to and from ground.
Therefore, the integrated circuits carried on a semiconductor device would ideally be electrically connected to conductive traces on carrier substrates such as printed circuit boards and thus to other semiconductor devices carried on the same or other such substrates by infinitesimally short conductors, eliminating impedance problems such as undesirable inductance and other conductor-induced system noise.
As a practical matter, however, as the capacity and speed of many semiconductor devices such as dynamic random access memories (DRAMs) has increased, the number of inputs and outputs (I/Os) to each semiconductor device has increased, requiring more numerous and complex external connections thereto, and in some instances requiring undesirably long lead frame lead fingers to place the inner lead ends in contact with, or in close proximity to, the bond pads serving as I/Os for the typical semiconductor device.
While lead inductance in IC packages has not traditionally been troublesome because slow signal frequencies of past devices render such inductance relatively insignificant, faster and ever-increasing signal frequencies of state-of-the-art electronic systems have substantially increased the practical significance of lead inductance. For example, at such faster signal frequencies, performance of integrated circuit dice using lead frames for external electrical connection is slower than desirable because the inductance associated with the lead fingers slows changes in signal currents through the leads, prolonging signal propagation through the leads. Further, digital signals propagating along the lead fingers are dispersing or xe2x80x9cspreading outxe2x80x9d because the so-called xe2x80x9cFourierxe2x80x9d components of various frequencies making up the digital signals propagate through the inductance associated with the lead fingers at different speeds, causing the signal components and thus the signals themselves to disperse along the lead fingers. While mild dispersion merely widens the digital signals without detrimental effect, severe dispersion can make the digital signals unrecognizable upon receipt. In addition, so-called xe2x80x9creflectionxe2x80x9d signals propagating along the lead fingers as a result of impedance mismatches between the lead fingers and associated semiconductor device or between the lead fingers and external circuitry, caused in part by lead-associated inductance can distort normal signals propagating along the lead fingers concurrently with the reflection signals. Further, magnetic fields created by signal currents propagating through the lead-associated inductance can induce currents in adjacent lead fingers, causing so-called xe2x80x9ccrosstalkxe2x80x9d noise on the later. While these various effects might be troublesome in any electronic system, the aforementioned trend toward lower voltage systems (currently 3.3 volts) and away from the traditional 5.0 volt systems increases their visibility and significance.
Certain currently-popular semiconductor device and package configurations serve to exacerbate the noise problems by favoring a large plurality of laterally adjacent lead fingers of substantial length. For example, so-called lead-over-chip (LOC) configurations typically place the bond pads of a semiconductor device in one or two rows extending along the longitudinal axis of the semiconductor device. To accommodate the centralized bond pad location for wire-bonding and at the same time eliminate the need for a conventional die-attach paddle as a physical semiconductor device support, LOC lead frames have been developed which employ lead fingers extending from the sides of the semiconductor device and over the active surface into close proximity with the bond pad row or rows. The semiconductor device is then supported from the undersides of the extending lead fingers, typically through an intervening polyimide film such as a Kapton(trademark) tape having an adhesive coating on its upper and lower surfaces, the film serving as a dielectric, an alpha barrier and a protective coating for the active surface.
While a mechanically desirable packaging concept, the LOC-type long, mutually parallel lead fingers running over the active surface become abusive in terms of unacceptably increasing real impedance as well as lead inductance (both self and mutual) in the circuit. These lead finger runs also increase signal reflection in the circuit due to transmission line effects and degrade signal integrity due to the aforementioned propagation delays, switching noise, and crosstalk. Further, elimination of the die-attach paddle also eliminates the potential for employing a ground plane under the semiconductor device without additional processing steps, and such a ground plane in any case would not alleviate the problems attendant to use of the long lead fingers extending over the semiconductor device""s active surface.
LOC configurations are merely one example of the type of packaging promoting the above-referenced undesirable noise phenomena. However, the same undesirable characteristics may be experienced with other lead frame configurations employing extended lead fingers, particularly large groups of such lead fingers in close mutual proximity. Such configurations include lead-under-chip (LUC) configurations, and configurations wherein a large number of leads extend from several sides of a semiconductor device to a single side or edge of a package, such as in a vertical surface mount package, or VSMP.
Packages have previously been configured in an attempt to reduce package noise of the type described above. For example, U.S. Pat. No. 5,214,845, assigned to the assignee of the present invention, employs a flexible, laminated sandwich assembly of an outer ground plane and an outer power plane dielectrically isolated from a series of conductive traces running therebetween. The traces and planes are connected to corresponding bond pads on the semiconductor device at one end, and to lead fingers on the other, as by thermocompression bonding (in the case of a TAB embodiment) or by wire bonds. Such an arrangement obviously doubles the number of required I/O connections, necessitating additional fabrication time and increasing the possibility of a faulty connection. Further, the flexible sandwich assembly constitutes an additional element of the package, increasing material cost.
Another approach to the problem is disclosed in U.S. Pat. No. 5,559,306, wherein metal plates are employed above and below leads extending to the exterior of plastic and ceramic packages to effect reduction of self and mutual inductance. However, such configurations as disclosed appear to require relatively complex fabrication techniques to locate and fix the plates relative to the semiconductor device and lead fingers or other conductors for subsequent transfer molding of a filled-polymer package thereabout, while the ceramic package embodiment is not cost-effective for high-volume, commercial packaging.
Accordingly, the inventors have recognized the need for a low-cost, reduced-inductance circuit configuration adaptable to current packaging designs and employing conventional and readily-available materials, equipment and fabrication techniques.
A semiconductor device package according to the present invention includes a substrate and a semiconductor device disposed upon the substrate.
A multi-layer lead frame of the leads-over-chip (LOC) type, leads-under-chip (LUC) type, or other type of lead frame arrangement provides an electrically conductive passageway from the semiconductor device disposed upon the substrate to devices that are external of the assembly. The multiple layers of the lead frame are joined by an interposed dielectric layer, which is also referred to as an insulator element, and each include a wide, electrically conductive bus. The layers may form a xe2x80x9cpaddlexe2x80x9d or xe2x80x9csupport platformxe2x80x9d to which a semiconductor device is secured. The bus of one of the lead frame layers is a power supply bus, while the bus of the other lead frame layer is a ground bus. The buses of each layer at least partially overlap to form a decoupling capacitor over a portion of the semiconductor device.
One of the lead frame layers includes a wide bus having one or more ground (Vss) lead fingers electrically connected thereto. Another of the lead frame layers includes a wide bus having one or more power (Vcc) lead fingers electrically connected thereto.
The decoupling capacitor reduces coupling and suppresses noise that is typically produced by the power supply components. Moreover, the juxtaposition and placement of the power supply lead fingers adjacent the sides of the semiconductor device package and away from (i.e., not interleaved with) the remaining lead fingers reduces the troublesome characteristics of mutual inductance and self inductance. Further, the placement of the buses in positions that would otherwise be occupied by long, adjacent, bent lead fingers also eliminates the magnetic fields that are typically generated by such lead fingers.
The multi-layer lead frame of the present invention also imparts at least a nominal heat sink effect to the semiconductor device, promoting the more even distribution of heat that is generated during operation of the semiconductor device than might be achieved through the lead fingers alone. This heat sink effect may be enhanced by increasing the mass of one or more of the lead frame buses, as by enhancing their thickness within the constraints of the package dimensions, or by configuring the buses with one or more portions extending to the exterior of the package. While this latter approach may render the device more susceptible to external radio-frequency interference, such an arrangement may be shielded, if necessary, by techniques known in the art. Such variation is especially useful in embodiments of the present invention wherein the semiconductor device is enclosed in a plastic, ceramic, or other type of package.
Should the device to be fabricated comprise a leads-over-chip device, conventional polyimide or other dielectric film or tape strips may be adhered to one side of the lead fingers, and the semiconductor devices subsequently adhered to the film by their active surfaces as known in the art prior to electrical connection of the semiconductor device and lead frames.
Those of ordinary skill in the art will recognize and appreciate that the multi-layered lead frame according to the present invention may be employed for an enhancement to any conventional plastic package design having adequate depth between the planes in which the lead fingers are positioned and the exterior surface of the package.
Other advantages of the present invention will become apparent to those of ordinary skill in the relevant art through a consideration of the appended drawings and the ensuing description.